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Integrated Circuit Systems, Inc.
ICS950901
Programmable Timing Control HubTM for P4TM
Recommended Application: VIA P4X266 chipset with PC133 or DDR memory. Output Features: * 2 - Pair of differential CPU clocks @ 3.3V * 1 - Pair of differential push pull CPU_CS clocks @ 2.5V * 3 - AGP @ 3.3V * 9 - PCI @ 3.3V * 2 - IOAPIC @ 2.5V * 1 - 48MHz @ 3.3V fixed * 1 - 24_48MHz @ 3.3V * 1 - REF @ 3.3V, 14.318MHz Features/Benefits: * Programmable output frequency. * Programmable output divider ratios. * Programmable output rise/fall time. * Programmable output skew. * Programmable spread percentage for EMI control. * Watchdog timer technology to reset system if system malfunctions. * Programmable watch dog safe frequency. * Support I2C Index read/write and block read/write operations. * For DDR and or PC133 SDRAM system use ICS93718 as the memory buffer. * Uses external 14.318MHz crystal. Key Specifications: * CPU_CS - CPU0: <250ps * CPU_CS - AGP: <250ps * PCI - PCI: <500ps * CPU - PCI: Min = 1.0ns, Typ = 2.0ns, Max = 4.0ns
Pin Configuration
1 *SEL24_48/REF VDDREF GND X1 X2 VDD48 **FS3/48MHz **FS2/24_48MHz GND *FS0/PCICLK_F **FS1/PCICLK0 PCICLK1 GND PCICLK2 PCICLK3 VDDPCI PCICLK4 PCICLK5 PCICLK6 GND PCICLK7 *PD# AGPCLK0 VDDAGP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 VDDAPIC (2.5V) GND IOAPIC0 IOAPIC1 GND VDDCPU_CS (2.5V) CPUCLKT_CS CPUCLKC_CS CPUCLKT_0 CPUCLKC_0 VDDCPU (3.3V) I REF GND CPUCLKT_1 CPUCLKC_1 Vtt_PWRGD# CPU_STOP#* PCI_STOP#* RESET# SDATA SCLK AGPCLK2 AGPCLK1 GND
48-Pin 300-mil SSOP
1. These outputs have 2X drive strength. * These inputs have a internal Pull-up resistor of 120K to VDD ** These inputs have a internal pull-down to GND
Frequency Table
FS 3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 FS 2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 FS 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 FS 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 C PUC LK MHz 66.67 100.00 133.33 200.00 100.90 103.00 107.00 110.00 133.90 137.33 140.00 142.66 145.33 146.66 153.33 160.00 AGP MHz 66.66 66.67 66.67 66.66 67.27 68.67 71.33 73.33 66.95 68.66 70.00 71.33 72.66 73.33 76.66 80.00 PC IC LK MHz 33.33 33.33 33.33 33.33 33.63 34.33 35.67 36.67 33.48 34.33 35.00 35.67 36.33 36.67 38.33 40.00
Block Diagram
PLL2 /2 X1 X2 XTAL XTAL OSC PLL1 Spread Spectrum Spectrum 48MHz 24_48MHz
REF
CPU DIVDER
Stop
CPUCLKT_(1:0) CPUCLKC_(1:0) CPUCLKT_CS CPUCLKC_CS IOAPIC IOAPIC (1:0)
CPU DIVDER
Stop
SEL24_48 SDA SDATA SCLK FS (3:0) PD# PCI_STOP# PCI_STOP# CPU_STOP# CPU_STOP# MULTI_SEL MULTI_SEL Vtt_PWRGD# Config. Reg. Control Logic
IOAPIC IOAPIC DIVDER
PCI DIVDER
Stop
PCICLK (7:0) PCICLK_F
AGP DIVDER
3
AGPCLK (2:0) RESET# I REF
0474F--05/25/05
ICS950901
Integrated Circuit Systems, Inc.
ICS950901
General Description
The ICS950901 is a single chip clock solution for desktop designs using the VIA P4X266 chipset with PC133 or DDR memory. with PC133 or DDR memory. When used with a fanout buffer such as the ICS93712, ICS93715 or the ICS93718 provides all the necessary clock signals for such a system. The ICS950901 is part of a whole new line of ICS clock generators and buffers called TCHTM (Timing Control Hub). This part incorporates ICS's newest clock technology which offers more robust features and functionality. Employing the use of a serially programmable I2C interface, this device can adjust the output clocks by configuring the frequency setting, the output divider ratios, selecting the ideal spread percentage, the output skew, the output strength, and enabling/disabling each individual output clock. M/N control can configure output frequency with resolution up to 0.1MHz increment.
Pin Description
PIN NUMBER 1 REF 2, 6, 16, 24, 38 4 5 VDD X1 X2 FS3 7 48MHz FS2 8 24_48MHz 3, 9, 13, 20, 25, 36, 44, 47 10 GND FS0 PCICLK_F 11 FS1 PCICLK0 22 PD# OUT PWR IN OUT IN OUT IN OUT OUT IN I/O OUT IN OUT OUT OUT OUT OUT PWR OUT PWR S e l e c t a bl e 2 4 o r 4 8 M H z o u t p u t . Ground pins for 3.3V supply. L o g i c i n p u t f r e q u e n c y s e l e c t b i t . I n p u t l a t c h e d a t p ow e r o n . 3.3V Free r unning PCI clock output L o g i c i n p u t f r e q u e n c y s e l e c t b i t . I n p u t l a t c h e d a t p ow e r o n . 3.3V PCI clock output. Asynchronous active low input pin used to power down the device into a low power state. The inter nal clocks are disabled and the VCO and the cr ystal are stopped. The latency of the power d ow n w i l l n o t b e g r e a t e r t h a n 3 m s. 3.3V PCI clock outputs. AGP outputs defined as 2X PCI. These may not be stopped. Clock pin for I2C circuitr y 5V tolerant. Data pin for I2C circuitr y 5V tolerant. Real time system reset signal for frequency value or watchdog timmer timeout. This signal is active low. This 3.3V LVTTL input is a level sensitive strobe used to determine when FS (3:0) is valid and ready to be sampled (active low). "Complementor y" clocks of differential pair CPU outputs. These are current outputs and external resistors are required for voltage bias. "True" clocks of differential pair CPU outputs. These are current outputs and external resistors are required for voltage bias. This pin establishes the reference current for the CPUCLK pairs. This pin requires a fixed p r e c i s i o n r e s i s t o r t i e d t o g r o u n d i n o r d e r t o e s t a bl i s h t h e a p p r o p r i a t e c u r r e n t . Complementor y"" clocks of differential pair CPU outputs. These are 2.5V push-pull outputs. True"" clocks of differential pair CPU outputs. These are 2.5V push-pull outputs. Power for CPUCLK_CS outputs 2.5V. 2.5V clock outputs Power for APIC clocks 2.5V. OUT IN 3.3V Fixed 48MHz clock output.. L o g i c i n p u t f r e q u e n c y s e l e c t b i t . I n p u t l a t c h e d a t p ow e r o n . OUT PWR IN OUT IN 3.3V, 14.318MHz reference clock output. 3.3V power supply. Cr ystal input, has inter nal load cap (33pF) and feedback resistor from X2. Cr ystal output, nominally 14.318MHz. Has inter nal load cap (33pF). L o g i c i n p u t f r e q u e n c y s e l e c t b i t . I n p u t l a t c h e d a t p ow e r o n . PIN NAME SEL24_48 TYPE IN Selects either 24 or 48MHz output. DESCRIPTION
21, 19, 18, 17, 15, 14 PCICLK (7:2) 27, 26, 23 28 29 30 33 34, 39 35, 40 37 41 42 43 45, 46 48 AGP (2:0) SCLK SDATA RESET# Vtt_PWRGD# CPUCLKC_(1:0) CPUCLKT_(1:0) I REF CPUCLKC_CS CPUCLKT_CS VDDCPU_CS (2.5V) IOAPIC (1:0) VDDAPIC (2.5V)
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Integrated Circuit Systems, Inc.
ICS950901
General I2C serial interface information How to Write:
Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) sends the data byte count = X ICS clock will acknowledge Controller (host) starts sending Byte N through Byte N + X -1 (see Note 2) * ICS clock will acknowledge each byte one at a time * Controller (host) sends a Stop bit * * * * * * * *
How to Read:
* * * * * * * * * * * * * * Controller (host) will send start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) will send a separate start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the data byte count = X ICS clock sends Byte N + X -1 ICS clock sends Byte 0 through byte X (if X(H) was written to byte 8). Controller (host) will need to acknowledge each byte Controllor (host) will send a not acknowledge bit Controller (host) will send a stop bit
Index Block Write Operation
Controller (Host) starT bit T Slave Address D2(H) WRite WR Beginning Byte = N ACK Data Byte Count = X ACK Beginning Byte N ACK X Byte ICS (Slave/Receiver)
Index Block Read Operation
Controller (Host) T starT bit Slave Address D2(H) WR WRite Beginning Byte = N ACK RT Repeat starT Slave Address D3(H) RD ReaD ACK Data Byte Count = X ACK Beginning Byte N X Byte ICS (Slave/Receiver)
ACK
ACK
Byte N + X - 1 ACK P stoP bit
ACK
Byte N + X - 1 N P Not acknowledge stoP bit
*See notes on the following page.
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Integrated Circuit Systems, Inc.
ICS950901
Byte 0: Functionality and frequency select register (Default=0)
Bi t Bit2
Description Bit7 Bit6 Bit5 Bit4 CPUCLK AGPCLK PCICLK MHz MHz MHz FS 3 FS 2 FS 1 FS 0 Spread %
PWD
Bi t (2,7:4)
Bi t 3 Bi t 1 Bi t 0
Notes:
0 0 0 0 0 66.67 66.66 33.33 +/- 0.30% Center Spread 0 0 0 0 1 100.00 66.67 33.33 +/- 0.30% Center Spread 0 0 0 1 0 133.33 66.67 33.33 +/- 0.30% Center Spread 33.33 +/- 0.30% Center Spread 0 0 0 1 1 200.00 66.66 0 0 1 0 0 100.90 67.27 33.63 +/- 0.30% Center Spread 0 0 1 0 1 103.00 68.67 34.33 +/- 0.30% Center Spread +/- 0.30% Center Spread 0 0 1 1 0 107.00 71.33 35.67 0 0 1 1 1 110.00 73.33 36.67 +/- 0.30% Center Spread 0 1 0 0 0 133.90 66.95 33.48 +/- 0.30% Center Spread +/- 0.30% Center Spread 0 1 0 0 1 137.33 68.66 34.33 0 1 0 1 0 140.00 70.00 35.00 +/- 0.30% Center Spread 0 1 0 1 1 142.66 71.33 35.67 +/- 0.30% Center Spread +/- 0.30% Center Spread 0 1 1 0 0 145.33 72.66 36.33 0 1 1 0 1 146.66 73.33 36.67 +/- 0.30% Center Spread 0 1 1 1 0 153.33 76.66 38.33 +/- 0.30% Center Spread +/- 0.30% Center Spread 0 1 1 1 1 160.00 80.00 40.00 1 0 0 0 0 66.67 66.66 33.33 0 to - 0.6% Down Spread 1 0 0 0 1 100.00 66.67 33.33 0 to - 0.6% Down Spread 0 to - 0.6% Down Spread 1 0 0 1 0 133.33 66.67 33.33 1 0 0 1 1 200.00 66.66 33.33 0 to - 0.6% Down Spread 1 0 1 0 0 66.67 66.66 33.33 +/- 0.50% Center Spread 1 0 1 0 1 100.00 66.67 33.33 +/- 0.50% Center Spread 133.33 66.67 33.33 +/- 0.50% Center Spread 1 0 1 1 0 1 0 1 1 1 200.00 66.66 33.33 +/- 0.30% Center Spread 1 1 0 0 0 201.00 67.00 33.50 +/- 0.30% Center Spread 203.00 67.67 33.83 +/- 0.30% Center Spread 1 1 0 0 1 1 1 0 1 0 205.00 68.33 34.17 +/- 0.30% Center Spread 1 1 0 1 1 207.00 69.00 34.50 +/- 0.30% Center Spread 209.00 69.67 34.83 +/- 0.30% Center Spread 1 1 1 0 0 1 1 1 0 1 211.00 70.33 35.17 +/- 0.30% Center Spread 1 1 1 1 0 213.00 71.00 35.50 +/- 0.30% Center Spread 71.67 35.83 +/- 0.30% Center Spread 1 1 1 1 1 215.00 0 - Frequency is selected by hardware select, latched inputs 1 - Frequency is selected by Bit 2,7:4 0 - Normal 1 - Spread spectrum enable 0 - Watch dog safe frequency will be selected by latch inputs 1 - Watch dog safe frequency will be programmed by Byte 10 bit (4:0)
Note 1
0 1 0
1. Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3.
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Integrated Circuit Systems, Inc.
ICS950901
Byte 1: CPU Active/Inactive Register (1 = enable, 0 = disable)
Bit Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Pin# 10 35, 34 40, 39 42, 41 PWD 1 1 1 0 0 1 1 1 Description (Reserved) PCICLK_F (Active/Inactive) (Reserved) (Reserved) (Reserved) CPUCLKT/C1 (Active/Inactive) CPUCLKT/C0 (Active/Inactive) CPUCLKT/C_CS (Active/Inactive)
Byte 2: PCI Active/Inactive Register (1 = enable, 0 = disable)
Bit Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Pin# 21 19 18 17 15 14 12 11
PWD 1 1 1 1 1 1 1 1
Description PCICLK7 PCICLK6 PCICLK5 PCICLK4 PCICLK3 PCICLK2 PCICLK1 PCICLK0 (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive)
Byte 3: Active/Inactive Register (1 = enable, 0 = disable)
Bit Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Pin# 1 46 45 23 26 27 PWD 1 1 1 1 1 1 1 1 Description Reserved SEL 24_48, 0=24Mhz 1=48MHz (Reserved) IOAPIC 0 IOAPIC 1 AGPCLK 0 AGPCLK 1 AGPCLK 2
Byte 4: Frequency Select Active/Inactive Register (1 = enable, 0 = disable)
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin# 7 8 1 PWD X X X X 1 1 0 1 Description Latched FS3# Latched FS2# Latched FS1# Latched FS0# 48MHz (Active/Inactive) 24_48MHz (Active/Inactive) Reserved REF (Active/Inactive)
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Integrated Circuit Systems, Inc.
ICS950901
Byte 5: Peripheral Active/Inactive Register (1 = enable, 0 = disable)
Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0
Pin# X X X X X X X X
PWD -
Description (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved)
Byte 6: Vendor ID Register (1 = enable, 0 = disable)
Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0 Name Revision ID Bit3 Revision ID Bit2 Revision ID Bit1 Revision ID Bit0 Vendor ID Bit3 Vendor ID Bit2 Vendor ID Bit1 Vendor ID Bit0 PWD X X X X 0 0 0 1 Description Revision ID values will be based on individual device's revision (Reserved) (Reserved) (Reserved) (Reserved)
Byte 7: Revision ID and Device ID Register
Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0
Name Device ID7 Device ID6 Device ID5 Device ID4 Device ID3 Device ID2 Device ID1 Device ID0
PWD Description 1 0 0 Device ID values will be based on individual device 1 "01h" in this case. 1 0 1 0
Byte 8: Byte Count Read Back Register
Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0
Name Byte7 Byte6 Byte5 Byte4 Byte3 Byte2 Byte1 Byte0
PWD Description 0 0 0 Note: Writing to this register will configure byte count and how 0 many bytes will be read back, default is 0FH = 15 bytes. 1 1 1 1
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Integrated Circuit Systems, Inc.
ICS950901
Byte 9: Watchdog Timer Count Register
Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0
Name WD7 WD6 WD5 WD4 WD3 WD2 WD1 WD0
PWD Description 0 0 0 The decimal representation of these 8 bits correspond to X * 0 290ms the watchdog timer will wait before it goes to alarm mode and reset the frequency to the safe setting. Default at power up is 1 8 * 290ms = 2.3 seconds. 0 0 0
Byte 10: Programming Enable bit 8 Watchdog Control Register
Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0
Name Program Enable WD Enable WD Alarm S F4 S F3 S F2 S F1 S F0
PWD 0 0 0 0 1 0 0 0
Description Programming Enable bit 0 = no programming. Frequencies are selected by HW latches or Byte0 1 = enable all I2C programing. Watchdog Enable bit. This bit will over write WDEN latched value. 0 = disable, 1 = Enable. Watchdog Alarm Status 0 = normal 1= alarm status Watchdog safe frequency bits. Writing to these bits will configure the safe frequency corrsponding to Byte 0 Bit 2, 7:4 table
Byte 11: VCO Frequency M Divider (Reference divider) Control Register
Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0
Name Ndiv 8 Mdiv 6 Mdiv 5 Mdiv 4 Mdiv 3 Mdiv 2 Mdiv 1 Mdiv 0
PWD X X X X X X X X
Description N divider bit 8
The decimal respresentation of Mdiv (6:0) corresposd to the reference divider value. Default at power up is equal to the latched inputs selection.
Byte 12: VCO Frequency N Divider (VCO divider) Control Register
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Name Ndiv 7 Ndiv 6 Ndiv 5 Ndiv 4 Ndiv 3 Ndiv 2 Ndiv 1 Ndiv 0
PWD Description X X X The decimal representation of Ndiv (8:0) correspond to the X VCO divider value. Default at power up is equal to the latched inputs selecton. Notice Ndiv 8 is located in Byte 11. X X X X
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Integrated Circuit Systems, Inc.
ICS950901
Byte 13: Spread Spectrum Control Register
Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0
Name SS 7 SS 6 SS 5 SS 4 SS 3 SS 2 SS 1 SS 0
PWD Description X X The Spread Spectrum (12:0) bit will program the spread X precentage. Spread precent needs to be calculated based on the X VCO frequency, spreading profile, spreading amount and spread X frequency. It is recommended to use ICS software for spread X programming. Default power on is latched FS divider. X X
Byte 14: Spread Spectrum Control Register
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Name Reserved Reserved Reserved SS 12 SS 11 SS 10 SS 9 SS 8
PWD X X X X X X X X
Description Reserved Reserved Reserved Spread Spectrum Bit 12 Spread Spectrum Bit 11 Spread Spectrum Bit 10 Spread Spectrum Bit 9 Spread Spectrum Bit 8
Byte 15: Output Divider Control Register
Bit Bit 7 B it 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Name CPU 0/1 Div 3 CPU 0/1 Div 2 CPU 0/1 Div 1 CPU 0/1 Div 0 CPU_CS Div 3 CPU_CS Div 2 CPU_CS Div 1 CPU_CS Div 0
PWD 0 1 0 1 0 1 0 1
Description CPU 0/1 clock divider ratio can be configured via these 4 bits individually. For divider selection table refer to Table 1. Default at power up is latched FS divider. CPU_CS clock divider ratio can be configured via these 4 bits individually. For divider selection table refer to Table 1. Default at power up is latched FS divider.
Byte 16: Output Divider Control Register
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Name AGP Div 3 AGP Div 2 AGP Div 1 AGP Div 0 APIC Div 3 APIC Div 2 APIC Div 1 APIC Div 0
PWD 0 1 0 1 0 1 0 1
Description AGP clock divider ratio can be configured via these 4 bits individually. For divider selection table refer to Table 1. Default at power up is latched FS divider. IOAPIC clock divider ratio can be configured via these 4 bits individually. For divider selection table refer to Table 2. Default at power up is latched FS divider.
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Integrated Circuit Systems, Inc.
ICS950901
Byte 17: Output Divider Control Register
Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0
Name AGP_INV APIC_INV CPU 0/1_INV CPU_CS_INV
PWD 0 0 0 0
Description AGP Phase Inversion bit APIC Phase Inversion bit CPU 0/1 Phase Inversion bit CPU_CS Phase Inversion bit
PCI Div 3 PCI Div 2 PCI Div 1 PCI Div 0
1 0 0 1
PCI clock divider ratio can be configured via these 4 bits individually. For divider selection table refer to Table 2. Default at power up is latched FS divider.
Table 1
Div (3:2) Div (1:0) 00 01 10 11 00 /2 /3 /5 /7 01 /4 /6 /10 /14 10 /8 /12 /20 /28 11 /16 /24 /40 /56
Table 2
Div (3:2) Div (1:0) 00 01 10 11 00 /4 /3 /5 /9 01 /8 /6 /10 /18 10 /16 /12 /20 /36 11 /32 /24 /40 /72
Byte 18: Group Skew Control Register
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name CPU_Skew 1 CPU_Skew 0 CPU_Skew 1 CPU_Skew 0 AGPCLK AGPCLK AGPCLK AGPCLK PWD 1 0 1 0 1 0 1 0 Description These 2 bits delay the CPUCLKC/T_CS with respect to CPUCLKC/T (1:0) 00 = 0ps 01 = 250ps 10 = 500ps 11 =750ps These 2 bits delay the CPUCLKC/T (1:0) clock with respect to CPUCLKC/T_CS 00 = 0ps 01 = 250ps 10 = 500ps 11 = 750ps Group Skew Control Group Skew Control Group Skew Control Group Skew Control
Byte 19: Group Skew Control Register
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Name IOAPIC IOAPIC IOAPIC IOAPIC PCICLK (7:0) PCICLK (7:0) PCICLK (7:0) PCICLK (7:0)
PWD 1 0 0 0 Group Skew Control 1 0 0 0
Description
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Integrated Circuit Systems, Inc.
ICS950901
Byte 20: Group Skew Control Register
Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0 Name PCI_Skew 3 PCI_Skew 2 PCI_Skew 1 PCI_Skew 0 PCIF_Skew 3 PCIF_Skew 2 PCIF_Skew 1 PCIF_Skew 0 PWD 1 0 0 0 1 0 0 0 Description These 4 bits can change the CPU to PCI (7:0) skew from 1.4ns 2.9ns. Default at power up is - 2.5ns. Each binary increment or decrement of Bits (3:0) will increase or decrease the delay of the PCI clocks by 100ps. These 4 bits can change the CPU to PCIF skew from 1.4ns 2.9ns. Default at power up is - 2.5ns. Each binary increment or decrement of Bit (3:0) will increase or decrease the delay of the PCI clocks by 100ps.
Byte 21: Slew Rate Control Register
Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0 Name PCIF_1_Slew 1 PCIF_1_Slew 0 PCIF_0_Slew 1 PCIF_0_Slew 0 AGP (2:1)_Slew 1 AGP (2:1)_Slew 1 AGP_0_Slew 1 AGP_0_Slew 0 PWD 0 1 0 1 0 1 0 1 Description PCIFclock slew rate control bits. 01 = strong:11 = normal; 10 = weak PCI clock slew rate control bits. 01 = strong: 11 = normal; 10 = weak AGP (2:1) clock slew rate control bits. 01 = strong: 11 = normal; 10 = weak AGP_0 clock slew rate control bits. 01 = strong: 11 = normal; 10 = weak
Byte 22: Slew Rate Control Register
Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0 Name REF Slew 1 REF Slew 0 PCI (7:4) Slew 1 PCI (7:4) Slew 0 PCI (3:1) Slew 1 PCI (3:1) Slew 0 PCI0 Slew 1 PCI0 Slew 0 PWD 0 1 0 1 0 1 0 1 Description REF clock slew rate control bits. 01 = strong: 11 = normal; 10 = weak PCI (6:4) clock slew rate control bits. 01 = strong: 11 = normal; 10 = weak PCI (3:1) clock slew rate control bits. 01 = strong: 11 = normal; 10 = weak PCI0 clock slew rate control bits. 01 = strong: 11 = normal; 10 = weak
Byte 23: Slew Rate Control Register
Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0 Name Reserved Reserved Reserved Reserved 48-24 Slew 1 48-24 Slew 0 48-24 Slew 1 48-24 Slew 0 PWD X X X X 0 1 0 1 Description Reserved Reserved 48-24 clock slew rate control bits. 01 = strong: 11 = normal; 10 = weak 48-24 clock slew rate control bits. 01 = strong: 11 = normal; 10 = weak
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ICS950901
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND -0.5 V to VDD +0.5 V Ambient Operating Temperature . . . . . . . . . . . . . . . . . 0C to +70C Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to +150C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters. TA = 0 - 70C; Supply Voltage VDD = 3.3 V + - 5% (unless otherwise stated) PARAMETER Input High Voltage Input Low Voltage Input High Current Input Low Current Input Low Current Operating Supply Current Power Down Supply Current Input frequency Pin Inductance Input Capacitance1 Transition Time1 Settling Time1 Clk Stabilization1 SYMBOL Vih Vil Iih Iil1 IIL2 IDD3.3OP CONDITIONS MIN 2 VSS-0.3 -5 -5 -200 TYP MAX VDD+0.3 0.8 5 UNITS V V mA mA mA mA mA mA mA MHz nH pF pF pF ms ms ms ns ns
Delay 1 Guarenteed by design, not 100% tested in production.
IDD3.3PD Fi Lpin CIN Cout CINX Ttrans Ts TSTAB tPZH,tPZH tPLZ,tPZH
Vin = VDD Vin = 0 V; Inputs with no pull-up resistors Vin = 0 V; Inputs with no pull-up resistors Cl = 0 pF; Select @ 66M Cl = Full load @ 133.3 MHz IREF=2.32mA IREF= 5mA VDD = 3.3 V; Logic Inputs Output pin capacitance X1 & X2 pins To 1st crossing of target Freq. From 1st crossing to 1% target Freq. From VDD = 3.3V to 1% target Freq. output enable delay (all outputs) output disable delay (all outputs)
181 13
100 280 20 37 7 5 6 45 3 3 3 10 10
27
1 1
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ICS950901
Electrical Characteristic - CPUCLKC/T TA = 0 - 70 C; VDD = 3.3 V +/-5%; (unless otherwise stated) PARAMETER SYMBOL CONDITIONS Current Source Output Impedance Zo Vo = Vx Vr = 475W +1%; IREF=2.32mA; Ioh = Output High Voltage Voh 6*IREF Output High Current Ioh Rise Time1 tr Vol = 20%, Voh = 80%, 0.175 - 0.525 V
MIN 3000
TYP
MAX
UNITS
0.71 -13.92 175 45 45 263 50 51 55 105
1.2
V mA
700 55 55 150 200
ps % % ps ps
Differential Crossover Vx dt Vt = 50% Duty Cycle1 Skew1, CPU to CPU tsk Vt = 50% Jitter, Cycle-to-cycle1 tjcyc-cyc Vt = V x Notes: 1 - Guaranteed by design, not 100% tested in production.
Electrical Characteristics - CPUCLKTC_CS TA = 0 - 70 C; VDD = 2.5V +/-5%; CL = 20 pF (unless otherwise stated) PARAMETER SYMBOL CONDITIONS Ioh = -12.0 mA Output High Voltage Voh2b Iol = 12 mA Output Low Voltage Vol2b Output High Current Ioh2b Voh = 1.7 V Vol = 0.7 V Output Low Current I ol2b Rise Time tr2B Vol = 0.4 V, Voh = 2.0 V Differential Crossover Vx Duty Cycle dt2B Vt = 1.25 V, Typ: crossing Vt = 1.25 V Skew tsk2B Jitter, Cycle-to-cycle tjcyc-cyc2B Vt = 1.25 V Vt = 1.25 V Jitter, One Sigma tj1s2B Vt = 1.25 V tjabs2B Jitter, Absolute
1Guaranteed
MIN 2
TYP
MAX 0.4 -19
19 45 45 0.75 50 50.9 155 -250 1.6 55 55 175 250 150 250
UNITS V V mA mA ns % % ps ps ps ps
by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
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Integrated Circuit Systems, Inc.
ICS950901
Electrical Characteristics - PCICLK TA = 0 - 70C; V DD = 3.3V +/-5%; CL = 10-30 pF (unless otherwise stated) PARAMETER Output Frequency Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Skew Jitter
1Guarenteed
SYMBOL F01 RDSN1 Voh1 Vol1 I oh1 I ol1 tr1 tf1 dt1 t sk1 tjcyc-cyc
CONDITIONS Vo = VDD*(0.5) Ioh = -1 mA Iol = 1 mA VOH@ MIN = 1.0 V, V OH@ MAX = 3.135 V VOL@ MIN = 1.95 V, V OL@ MAX= 0.4 V Vol = 0.4 V, V oh = 2.4 V Voh = 2.4 V, Vol = 0.4 V Vt = 1.5 V Vt = 1.5 V Vt = 1.5 V
MIN 12 2.4 -33 30 0.5 0.5 45
TYP 33.33
MAX 55 0.55 -33 38 2 2 55 500 250
UNITS MHz V V mA mA ns ns % ps ps
1.91 1.68 49.7 332 116
by design, not 100% tested in production.
Electrical Characteristics - AGP TA = 0 - 70C; V DD = 3.3 V +/-5%; CL = 10-30 pF (unless otherwise stated) PARAMETER Output Impedance Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Skew Jitter
1Guarenteed
SYMBOL RDSP1 RDSN1 V OH1 VOL1 I OH1 IOL1 t r1 t f1 dt1 t sk1 t jcyc-cyc
CONDITIONS V o = V DD*(0.5) V o = V DD*(0.5) I oh = -1 mA I ol = 1 mA V OH@ MIN = 1.0 V, V OH@ MAX = 3.135 V V OL@ MIN = 1.95 V, V OL@ MAX= 0.4 V V ol = 4 V, V oh = 2.4 V V oh = 2.4 V, Vol = 0.4 V V t = 1.5 V V t = 1.5 V V t = 1.5 V
MIN 12 12 2.4 -33 30 0.5 0.5 45
TYP
MAX 55 55 0.55 -33 38 2 2 55 175 500
UNITS V V mA mA ns ns % ps ps
1.16 1.22 51.8 84
by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
13
Integrated Circuit Systems, Inc.
ICS950901
Electrical Characteristics - IOAPIC TA = 0 - 70 C; VDD = 3.3V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 (unless otherwise stated) PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time1 Fall Time1 Duty Cycle1 Jitter, One Sigma1 Jitter, Absolute1 Jitter, Cycle to Cycle
1Guaranteed
SYMBOL Voh4b Vol4b Ioh4b I ol4b Tr4B Tf4B Dt4B Tj1s4B Tjabs4B
Normal
CONDITIONS I oh = -12 mA I ol = 12 mA Voh = 1.7 V Vol = 0.7 V Vol = 0.4 V, VOH = 2.0 V Voh = 2.0 V, VOL = 0.4 V Vt = 1.25 V Vt = 1.25 V Vt = 1.25 V Vt = 1.25 V
MIN 2
TYP
MAX 0.4 -19
19 1.16 1.09 49.9 2 2 55 0.5 1 250
45 -1
89
UNITS V V mA mA ns ns % ns ns ps
by design, not 100% tested in production.
Electrical Characteristics - 48MHz
TA = 0 - 70C; VDD = 3.3V +/-5%; CL = 30 pF (unless otherwise stated) PARAMETER Output Frequency Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current 48DOT Rise Time 48DOT Fall Time VCH 48 USB Rise Time VCH 48 USB Fall Time 48 DOT to 48 USB Skew Duty Cycle Jitter
1Guarenteed
SYMBOL FO RDSN1 V OH1 V OL1 IOH1 IOL1 t r1 t f1 tr t f1 tskew1 dt1 t jcyc-cyc
CONDITIONS V o = VDD*(0.5) V o = VDD*(0.5) Ioh = -1 mA I ol = 1 mA VOH@ MIN = 1.0 V, VOH@ MAX = 3.135 V VOL@ MIN = 1.95 V, VOL@ MAX= 0.4 V Vol = 0.4 V, V oh = = 2.4 V Voh = 2.4 V, Vol = 0.4 V Vol = 0.4 V, V oh = 2.4 V Voh = 2.4 V, Vol = 0.4 V V t = 1.5 V V t = 1.5 V V t = 1.5 V
MIN 12 2.4
TYP 48
MAX 55 0.55
UNITS MHz V V mA mA ns ns ns ns ns % ps
-29 29 0.5 0.5 1 1
-23 27 1 1 2 2 1 55 350
1.32 1.28 1.32 1.26 0.3
45
52.7 119
by design, not 100% tested in production
Third party brands and names are the property of their respective owners.
14
Integrated Circuit Systems, Inc.
ICS950901
Electrical Characteristics - REF TA = 0 - 70C; VDD = 3.3 V +/-5%; CL =10-20 pF (unless otherwise stated) PARAMETER SYMBOL CONDITIONS Output Frequency Fo1 Output Impedance Rdsp1 V o = V DD*(0.5) I oh = -1 mA Output High Voltage V oh1 I ol = 1 mA Output Low Voltage V ol1 Output High Current I oh1 V OH@ MIN = 1.0 V, V OH@ MAX = 3.135 V Output Low Current I ol1 V OL@ MIN = 1.95 V, VOL@ MAX= 0.4 V ol = 0.4 V, V oh = 2.4 V Rise Time t r1 Fall Time t f1 V oh = 2.4 V, V OL = 0.4 V Duty Cycle dt1 V t = 1.5 V tjcyc-cyc V t = 1.5 V Jitter
1Guarenteed
MIN 20 2.4 -29 29 1 1 45
TYP
MAX 60 0.4 -23 27 4 4 55 500
UNITS MHz V V mA mA ns ns % ps
0.89 0.72 54.6 234
by design, not 100% tested in production.
Electrical Characteristics - CPU
TA = 0 - 70C, VDDL = 2.5 V +/-5%; CL = 10 - 20 pF (unless otherwise stated) PARAMETER Output Impedance Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Skew Jitter
1
SYMBOL RDSP2B RDSN2B V OH2B V OL2B I OH2B IOL2B t r2B1 t f2B
1 1 1 1 1 1
CONDITIONS VO = VDD*(0.5) VO = VDD*(0.5) IOH = -1 mA IOL = 1 mA VOH @MIN= 1.0V , VOH@ MAX= 2.375V VOL @MIN= 1.2V , VOL@ MAX= 0.3V VOL = 0.4 V, VOH = 2.0 V VOH = 0.4 V, VOL = 2.0 V VT = 1.25 V VT = 1.25 V VT = 1.25 V
MIN 13.5 13.5 2 -27 27 0.4 0.4 45
TYP
MAX UNITS 45 45 0.4 -27 30 1.6 1.6 V V mA mA ns ns ns ps ps
dt2B
50
55 175 250
tsk2B
t jcyc-cyc
Guarenteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
15
Integrated Circuit Systems, Inc.
ICS950901
Shared Pin Operation Input/Output Pins
The I/O pins designated by (input/output) serve as dual signal functions to the device. During initial power-up, they act as input pins. The logic level (voltage) that is present on these pins at this time is read and stored into a 5-bit internal data latch. At the end of Power-On reset, (see AC characteristics for timing values), the device changes the mode of operations for these pins to an output function. In this mode the pins produce the specified buffered clocks to external loads. To program (load) the internal configuration register for these pins, a resistor is connected to either the VDD (logic 1) power supply or the GND (logic 0) voltage potential. A 10 Kilohm (10K) resistor is used to provide both the solid CMOS programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. Figure 1 shows a means of implementing this function when a switch or 2 pin header is used. With no jumper is installed the pin will be pulled high. With the jumper in place the pin will be pulled low. If programmability is not necessary, than only a single resistor is necessary. The programming resistors should be located close to the series termination resistor to minimize the current loop area. It is more important to locate the series termination resistor close to the driver than the programming resistor.
Programming Header Via to Gnd Device Pad
Via to VDD 2K W
8.2K W Clock trace to load Series Term. Res.
Fig. 1
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16
Integrated Circuit Systems, Inc.
ICS950901
Power Down Waveform
0ns 1 25ns 50ns 2
VCO Internal CPU 100MHz 3.3V 66MHz PCI 33MHz APIC 16.7MHz PD# SDRAM 100MHz REF 14.318MHZ 48MHZ
Note
1. After PD# is sampled active (Low) for 2 consective rising edges of CPUCLKs, all the output clocks are driven Low on their next High to Low tranistiion. 2. Power-up latency <3ms. 3. Waveform shown for 100MHz
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17
Integrated Circuit Systems, Inc.
ICS950901
0ns
10ns
20ns
30ns
40ns
Cycle Repeats
CPU 66MHz CPU 100MHz CPU 133MHz
SDRAM 100MHz SDRAM 133MHz
3.5V 66MHz PCI 33MHz APIC 16.7MHz REF 14.318MHz USB 48MHz
Group Offset Waveforms
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18
Integrated Circuit Systems, Inc.
ICS950901
N
c
SYMBOL
L
INDEX AREA
E1
E
12 D h x 45
a
A A1
A A1 b c D E E1 e h L N
In Millimeters COMMON DIMENSIONS MIN MAX 2.41 2.80 0.20 0.40 0.20 0.34 0.13 0.25 SEE VARIATIONS 10.03 10.68 7.40 7.60 0.635 BASIC 0.38 0.64 0.50 1.02 SEE VARIATIONS 0 8 VARIATIONS D mm. MIN MAX 15.75 16.00
In Inches COMMON DIMENSIONS MIN MAX .095 .110 .008 .016 .008 .0135 .005 .010 SEE VARIATIONS .395 .420 .291 .299 0.025 BASIC .015 .025 .020 .040 SEE VARIATIONS 0 8
-Ce
b SEATING PLANE .10 (.004) C
N 48
10-0034
D (inch) MIN .620 MAX .630
Reference Doc.: JEDEC Publication 95, MO-118
300 mil SSOP Package
Ordering Information
ICS950901yFLFT
Example:
ICS XXXX y F LF - T
Designation for tape and reel packaging RoHS Compliant (Optional) Package Type F=SSOP Revision Designator (will not correlate with datasheet revision) Device Type (consists of 3 to 7 digit numbers)
Registered Company
Prefix ICS, AV = Standard Device
9001
For more information on Integrated Circuit Systems Inc. or any of our products please visit our web site at: http://www.icst.com
19
Integrated Circuit Systems, Inc.
ICS950901
Revision History
Rev. F Issue Date Description 5/25/2005 Added LF Ordering Information. Page # 19
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20

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